;
; File Name: cyfitteriar.inc
; 
; PSoC Creator  4.2
;
; Description:
; 
;
;-------------------------------------------------------------------------------
; Copyright (c) 2007-2018 Cypress Semiconductor.  All rights reserved.
; You may use this file only in accordance with the license, terms, conditions, 
; disclaimers, and limitations in the end user license agreement accompanying 
; the software package with which this file was provided.
;-------------------------------------------------------------------------------

#ifndef INCLUDED_CYFITTERIAR_INC
#define INCLUDED_CYFITTERIAR_INC
    INCLUDE cydeviceiar_trm.inc

/* nss */
nss__0__DR EQU CYREG_GPIO_PRT4_DR
nss__0__DR_CLR EQU CYREG_GPIO_PRT4_DR_CLR
nss__0__DR_INV EQU CYREG_GPIO_PRT4_DR_INV
nss__0__DR_SET EQU CYREG_GPIO_PRT4_DR_SET
nss__0__HSIOM EQU CYREG_HSIOM_PORT_SEL4
nss__0__HSIOM_MASK EQU 0x0000F000
nss__0__HSIOM_SHIFT EQU 12
nss__0__INTCFG EQU CYREG_GPIO_PRT4_INTR_CFG
nss__0__INTR EQU CYREG_GPIO_PRT4_INTR
nss__0__INTR_CFG EQU CYREG_GPIO_PRT4_INTR_CFG
nss__0__INTSTAT EQU CYREG_GPIO_PRT4_INTR
nss__0__MASK EQU 0x08
nss__0__PC EQU CYREG_GPIO_PRT4_PC
nss__0__PC2 EQU CYREG_GPIO_PRT4_PC2
nss__0__PORT EQU 4
nss__0__PS EQU CYREG_GPIO_PRT4_PS
nss__0__SHIFT EQU 3
nss__DR EQU CYREG_GPIO_PRT4_DR
nss__DR_CLR EQU CYREG_GPIO_PRT4_DR_CLR
nss__DR_INV EQU CYREG_GPIO_PRT4_DR_INV
nss__DR_SET EQU CYREG_GPIO_PRT4_DR_SET
nss__INTCFG EQU CYREG_GPIO_PRT4_INTR_CFG
nss__INTR EQU CYREG_GPIO_PRT4_INTR
nss__INTR_CFG EQU CYREG_GPIO_PRT4_INTR_CFG
nss__INTSTAT EQU CYREG_GPIO_PRT4_INTR
nss__MASK EQU 0x08
nss__PC EQU CYREG_GPIO_PRT4_PC
nss__PC2 EQU CYREG_GPIO_PRT4_PC2
nss__PORT EQU 4
nss__PS EQU CYREG_GPIO_PRT4_PS
nss__SHIFT EQU 3

/* dio1 */
dio1__0__DR EQU CYREG_GPIO_PRT4_DR
dio1__0__DR_CLR EQU CYREG_GPIO_PRT4_DR_CLR
dio1__0__DR_INV EQU CYREG_GPIO_PRT4_DR_INV
dio1__0__DR_SET EQU CYREG_GPIO_PRT4_DR_SET
dio1__0__HSIOM EQU CYREG_HSIOM_PORT_SEL4
dio1__0__HSIOM_MASK EQU 0x0F000000
dio1__0__HSIOM_SHIFT EQU 24
dio1__0__INTCFG EQU CYREG_GPIO_PRT4_INTR_CFG
dio1__0__INTR EQU CYREG_GPIO_PRT4_INTR
dio1__0__INTR_CFG EQU CYREG_GPIO_PRT4_INTR_CFG
dio1__0__INTSTAT EQU CYREG_GPIO_PRT4_INTR
dio1__0__MASK EQU 0x40
dio1__0__PC EQU CYREG_GPIO_PRT4_PC
dio1__0__PC2 EQU CYREG_GPIO_PRT4_PC2
dio1__0__PORT EQU 4
dio1__0__PS EQU CYREG_GPIO_PRT4_PS
dio1__0__SHIFT EQU 6
dio1__DR EQU CYREG_GPIO_PRT4_DR
dio1__DR_CLR EQU CYREG_GPIO_PRT4_DR_CLR
dio1__DR_INV EQU CYREG_GPIO_PRT4_DR_INV
dio1__DR_SET EQU CYREG_GPIO_PRT4_DR_SET
dio1__INTCFG EQU CYREG_GPIO_PRT4_INTR_CFG
dio1__INTR EQU CYREG_GPIO_PRT4_INTR
dio1__INTR_CFG EQU CYREG_GPIO_PRT4_INTR_CFG
dio1__INTSTAT EQU CYREG_GPIO_PRT4_INTR
dio1__MASK EQU 0x40
dio1__PC EQU CYREG_GPIO_PRT4_PC
dio1__PC2 EQU CYREG_GPIO_PRT4_PC2
dio1__PORT EQU 4
dio1__PS EQU CYREG_GPIO_PRT4_PS
dio1__SHIFT EQU 6
dio1__SNAP EQU CYREG_GPIO_PRT4_INTR

/* SPI_1 */
SPI_1_miso_m__0__DR EQU CYREG_GPIO_PRT4_DR
SPI_1_miso_m__0__DR_CLR EQU CYREG_GPIO_PRT4_DR_CLR
SPI_1_miso_m__0__DR_INV EQU CYREG_GPIO_PRT4_DR_INV
SPI_1_miso_m__0__DR_SET EQU CYREG_GPIO_PRT4_DR_SET
SPI_1_miso_m__0__HSIOM EQU CYREG_HSIOM_PORT_SEL4
SPI_1_miso_m__0__HSIOM_GPIO EQU 0
SPI_1_miso_m__0__HSIOM_I2C EQU 14
SPI_1_miso_m__0__HSIOM_I2C_SDA EQU 14
SPI_1_miso_m__0__HSIOM_MASK EQU 0x000000F0
SPI_1_miso_m__0__HSIOM_SHIFT EQU 4
SPI_1_miso_m__0__HSIOM_SPI EQU 15
SPI_1_miso_m__0__HSIOM_SPI_MISO EQU 15
SPI_1_miso_m__0__HSIOM_UART EQU 9
SPI_1_miso_m__0__HSIOM_UART_TX EQU 9
SPI_1_miso_m__0__INTCFG EQU CYREG_GPIO_PRT4_INTR_CFG
SPI_1_miso_m__0__INTR EQU CYREG_GPIO_PRT4_INTR
SPI_1_miso_m__0__INTR_CFG EQU CYREG_GPIO_PRT4_INTR_CFG
SPI_1_miso_m__0__INTSTAT EQU CYREG_GPIO_PRT4_INTR
SPI_1_miso_m__0__MASK EQU 0x02
SPI_1_miso_m__0__PC EQU CYREG_GPIO_PRT4_PC
SPI_1_miso_m__0__PC2 EQU CYREG_GPIO_PRT4_PC2
SPI_1_miso_m__0__PORT EQU 4
SPI_1_miso_m__0__PS EQU CYREG_GPIO_PRT4_PS
SPI_1_miso_m__0__SHIFT EQU 1
SPI_1_miso_m__DR EQU CYREG_GPIO_PRT4_DR
SPI_1_miso_m__DR_CLR EQU CYREG_GPIO_PRT4_DR_CLR
SPI_1_miso_m__DR_INV EQU CYREG_GPIO_PRT4_DR_INV
SPI_1_miso_m__DR_SET EQU CYREG_GPIO_PRT4_DR_SET
SPI_1_miso_m__INTCFG EQU CYREG_GPIO_PRT4_INTR_CFG
SPI_1_miso_m__INTR EQU CYREG_GPIO_PRT4_INTR
SPI_1_miso_m__INTR_CFG EQU CYREG_GPIO_PRT4_INTR_CFG
SPI_1_miso_m__INTSTAT EQU CYREG_GPIO_PRT4_INTR
SPI_1_miso_m__MASK EQU 0x02
SPI_1_miso_m__PC EQU CYREG_GPIO_PRT4_PC
SPI_1_miso_m__PC2 EQU CYREG_GPIO_PRT4_PC2
SPI_1_miso_m__PORT EQU 4
SPI_1_miso_m__PS EQU CYREG_GPIO_PRT4_PS
SPI_1_miso_m__SHIFT EQU 1
SPI_1_mosi_m__0__DR EQU CYREG_GPIO_PRT4_DR
SPI_1_mosi_m__0__DR_CLR EQU CYREG_GPIO_PRT4_DR_CLR
SPI_1_mosi_m__0__DR_INV EQU CYREG_GPIO_PRT4_DR_INV
SPI_1_mosi_m__0__DR_SET EQU CYREG_GPIO_PRT4_DR_SET
SPI_1_mosi_m__0__HSIOM EQU CYREG_HSIOM_PORT_SEL4
SPI_1_mosi_m__0__HSIOM_GPIO EQU 0
SPI_1_mosi_m__0__HSIOM_I2C EQU 14
SPI_1_mosi_m__0__HSIOM_I2C_SCL EQU 14
SPI_1_mosi_m__0__HSIOM_MASK EQU 0x0000000F
SPI_1_mosi_m__0__HSIOM_SHIFT EQU 0
SPI_1_mosi_m__0__HSIOM_SPI EQU 15
SPI_1_mosi_m__0__HSIOM_SPI_MOSI EQU 15
SPI_1_mosi_m__0__HSIOM_UART EQU 9
SPI_1_mosi_m__0__HSIOM_UART_RX EQU 9
SPI_1_mosi_m__0__INTCFG EQU CYREG_GPIO_PRT4_INTR_CFG
SPI_1_mosi_m__0__INTR EQU CYREG_GPIO_PRT4_INTR
SPI_1_mosi_m__0__INTR_CFG EQU CYREG_GPIO_PRT4_INTR_CFG
SPI_1_mosi_m__0__INTSTAT EQU CYREG_GPIO_PRT4_INTR
SPI_1_mosi_m__0__MASK EQU 0x01
SPI_1_mosi_m__0__PC EQU CYREG_GPIO_PRT4_PC
SPI_1_mosi_m__0__PC2 EQU CYREG_GPIO_PRT4_PC2
SPI_1_mosi_m__0__PORT EQU 4
SPI_1_mosi_m__0__PS EQU CYREG_GPIO_PRT4_PS
SPI_1_mosi_m__0__SHIFT EQU 0
SPI_1_mosi_m__DR EQU CYREG_GPIO_PRT4_DR
SPI_1_mosi_m__DR_CLR EQU CYREG_GPIO_PRT4_DR_CLR
SPI_1_mosi_m__DR_INV EQU CYREG_GPIO_PRT4_DR_INV
SPI_1_mosi_m__DR_SET EQU CYREG_GPIO_PRT4_DR_SET
SPI_1_mosi_m__INTCFG EQU CYREG_GPIO_PRT4_INTR_CFG
SPI_1_mosi_m__INTR EQU CYREG_GPIO_PRT4_INTR
SPI_1_mosi_m__INTR_CFG EQU CYREG_GPIO_PRT4_INTR_CFG
SPI_1_mosi_m__INTSTAT EQU CYREG_GPIO_PRT4_INTR
SPI_1_mosi_m__MASK EQU 0x01
SPI_1_mosi_m__PC EQU CYREG_GPIO_PRT4_PC
SPI_1_mosi_m__PC2 EQU CYREG_GPIO_PRT4_PC2
SPI_1_mosi_m__PORT EQU 4
SPI_1_mosi_m__PS EQU CYREG_GPIO_PRT4_PS
SPI_1_mosi_m__SHIFT EQU 0
SPI_1_SCB__CTRL EQU CYREG_SCB0_CTRL
SPI_1_SCB__EZ_DATA0 EQU CYREG_SCB0_EZ_DATA0
SPI_1_SCB__EZ_DATA1 EQU CYREG_SCB0_EZ_DATA1
SPI_1_SCB__EZ_DATA10 EQU CYREG_SCB0_EZ_DATA10
SPI_1_SCB__EZ_DATA11 EQU CYREG_SCB0_EZ_DATA11
SPI_1_SCB__EZ_DATA12 EQU CYREG_SCB0_EZ_DATA12
SPI_1_SCB__EZ_DATA13 EQU CYREG_SCB0_EZ_DATA13
SPI_1_SCB__EZ_DATA14 EQU CYREG_SCB0_EZ_DATA14
SPI_1_SCB__EZ_DATA15 EQU CYREG_SCB0_EZ_DATA15
SPI_1_SCB__EZ_DATA16 EQU CYREG_SCB0_EZ_DATA16
SPI_1_SCB__EZ_DATA17 EQU CYREG_SCB0_EZ_DATA17
SPI_1_SCB__EZ_DATA18 EQU CYREG_SCB0_EZ_DATA18
SPI_1_SCB__EZ_DATA19 EQU CYREG_SCB0_EZ_DATA19
SPI_1_SCB__EZ_DATA2 EQU CYREG_SCB0_EZ_DATA2
SPI_1_SCB__EZ_DATA20 EQU CYREG_SCB0_EZ_DATA20
SPI_1_SCB__EZ_DATA21 EQU CYREG_SCB0_EZ_DATA21
SPI_1_SCB__EZ_DATA22 EQU CYREG_SCB0_EZ_DATA22
SPI_1_SCB__EZ_DATA23 EQU CYREG_SCB0_EZ_DATA23
SPI_1_SCB__EZ_DATA24 EQU CYREG_SCB0_EZ_DATA24
SPI_1_SCB__EZ_DATA25 EQU CYREG_SCB0_EZ_DATA25
SPI_1_SCB__EZ_DATA26 EQU CYREG_SCB0_EZ_DATA26
SPI_1_SCB__EZ_DATA27 EQU CYREG_SCB0_EZ_DATA27
SPI_1_SCB__EZ_DATA28 EQU CYREG_SCB0_EZ_DATA28
SPI_1_SCB__EZ_DATA29 EQU CYREG_SCB0_EZ_DATA29
SPI_1_SCB__EZ_DATA3 EQU CYREG_SCB0_EZ_DATA3
SPI_1_SCB__EZ_DATA30 EQU CYREG_SCB0_EZ_DATA30
SPI_1_SCB__EZ_DATA31 EQU CYREG_SCB0_EZ_DATA31
SPI_1_SCB__EZ_DATA4 EQU CYREG_SCB0_EZ_DATA4
SPI_1_SCB__EZ_DATA5 EQU CYREG_SCB0_EZ_DATA5
SPI_1_SCB__EZ_DATA6 EQU CYREG_SCB0_EZ_DATA6
SPI_1_SCB__EZ_DATA7 EQU CYREG_SCB0_EZ_DATA7
SPI_1_SCB__EZ_DATA8 EQU CYREG_SCB0_EZ_DATA8
SPI_1_SCB__EZ_DATA9 EQU CYREG_SCB0_EZ_DATA9
SPI_1_SCB__I2C_CFG EQU CYREG_SCB0_I2C_CFG
SPI_1_SCB__I2C_CTRL EQU CYREG_SCB0_I2C_CTRL
SPI_1_SCB__I2C_M_CMD EQU CYREG_SCB0_I2C_M_CMD
SPI_1_SCB__I2C_S_CMD EQU CYREG_SCB0_I2C_S_CMD
SPI_1_SCB__I2C_STATUS EQU CYREG_SCB0_I2C_STATUS
SPI_1_SCB__INTR_CAUSE EQU CYREG_SCB0_INTR_CAUSE
SPI_1_SCB__INTR_I2C_EC EQU CYREG_SCB0_INTR_I2C_EC
SPI_1_SCB__INTR_I2C_EC_MASK EQU CYREG_SCB0_INTR_I2C_EC_MASK
SPI_1_SCB__INTR_I2C_EC_MASKED EQU CYREG_SCB0_INTR_I2C_EC_MASKED
SPI_1_SCB__INTR_M EQU CYREG_SCB0_INTR_M
SPI_1_SCB__INTR_M_MASK EQU CYREG_SCB0_INTR_M_MASK
SPI_1_SCB__INTR_M_MASKED EQU CYREG_SCB0_INTR_M_MASKED
SPI_1_SCB__INTR_M_SET EQU CYREG_SCB0_INTR_M_SET
SPI_1_SCB__INTR_RX EQU CYREG_SCB0_INTR_RX
SPI_1_SCB__INTR_RX_MASK EQU CYREG_SCB0_INTR_RX_MASK
SPI_1_SCB__INTR_RX_MASKED EQU CYREG_SCB0_INTR_RX_MASKED
SPI_1_SCB__INTR_RX_SET EQU CYREG_SCB0_INTR_RX_SET
SPI_1_SCB__INTR_S EQU CYREG_SCB0_INTR_S
SPI_1_SCB__INTR_S_MASK EQU CYREG_SCB0_INTR_S_MASK
SPI_1_SCB__INTR_S_MASKED EQU CYREG_SCB0_INTR_S_MASKED
SPI_1_SCB__INTR_S_SET EQU CYREG_SCB0_INTR_S_SET
SPI_1_SCB__INTR_SPI_EC EQU CYREG_SCB0_INTR_SPI_EC
SPI_1_SCB__INTR_SPI_EC_MASK EQU CYREG_SCB0_INTR_SPI_EC_MASK
SPI_1_SCB__INTR_SPI_EC_MASKED EQU CYREG_SCB0_INTR_SPI_EC_MASKED
SPI_1_SCB__INTR_TX EQU CYREG_SCB0_INTR_TX
SPI_1_SCB__INTR_TX_MASK EQU CYREG_SCB0_INTR_TX_MASK
SPI_1_SCB__INTR_TX_MASKED EQU CYREG_SCB0_INTR_TX_MASKED
SPI_1_SCB__INTR_TX_SET EQU CYREG_SCB0_INTR_TX_SET
SPI_1_SCB__RX_CTRL EQU CYREG_SCB0_RX_CTRL
SPI_1_SCB__RX_FIFO_CTRL EQU CYREG_SCB0_RX_FIFO_CTRL
SPI_1_SCB__RX_FIFO_RD EQU CYREG_SCB0_RX_FIFO_RD
SPI_1_SCB__RX_FIFO_RD_SILENT EQU CYREG_SCB0_RX_FIFO_RD_SILENT
SPI_1_SCB__RX_FIFO_STATUS EQU CYREG_SCB0_RX_FIFO_STATUS
SPI_1_SCB__RX_MATCH EQU CYREG_SCB0_RX_MATCH
SPI_1_SCB__SPI_CTRL EQU CYREG_SCB0_SPI_CTRL
SPI_1_SCB__SPI_STATUS EQU CYREG_SCB0_SPI_STATUS
SPI_1_SCB__SS0_POSISTION EQU 0
SPI_1_SCB__SS1_POSISTION EQU 1
SPI_1_SCB__SS2_POSISTION EQU 2
SPI_1_SCB__SS3_POSISTION EQU 3
SPI_1_SCB__STATUS EQU CYREG_SCB0_STATUS
SPI_1_SCB__TX_CTRL EQU CYREG_SCB0_TX_CTRL
SPI_1_SCB__TX_FIFO_CTRL EQU CYREG_SCB0_TX_FIFO_CTRL
SPI_1_SCB__TX_FIFO_STATUS EQU CYREG_SCB0_TX_FIFO_STATUS
SPI_1_SCB__TX_FIFO_WR EQU CYREG_SCB0_TX_FIFO_WR
SPI_1_SCB__UART_CTRL EQU CYREG_SCB0_UART_CTRL
SPI_1_SCB__UART_FLOW_CTRL EQU CYREG_SCB0_UART_FLOW_CTRL
SPI_1_SCB__UART_RX_CTRL EQU CYREG_SCB0_UART_RX_CTRL
SPI_1_SCB__UART_RX_STATUS EQU CYREG_SCB0_UART_RX_STATUS
SPI_1_SCB__UART_TX_CTRL EQU CYREG_SCB0_UART_TX_CTRL
SPI_1_SCBCLK__CTRL_REGISTER EQU CYREG_PERI_PCLK_CTL0
SPI_1_SCBCLK__DIV_ID EQU 0x00000040
SPI_1_SCBCLK__DIV_REGISTER EQU CYREG_PERI_DIV_16_CTL0
SPI_1_SCBCLK__PA_DIV_ID EQU 0x000000FF
SPI_1_sclk_m__0__DR EQU CYREG_GPIO_PRT4_DR
SPI_1_sclk_m__0__DR_CLR EQU CYREG_GPIO_PRT4_DR_CLR
SPI_1_sclk_m__0__DR_INV EQU CYREG_GPIO_PRT4_DR_INV
SPI_1_sclk_m__0__DR_SET EQU CYREG_GPIO_PRT4_DR_SET
SPI_1_sclk_m__0__HSIOM EQU CYREG_HSIOM_PORT_SEL4
SPI_1_sclk_m__0__HSIOM_GPIO EQU 0
SPI_1_sclk_m__0__HSIOM_MASK EQU 0x00000F00
SPI_1_sclk_m__0__HSIOM_SHIFT EQU 8
SPI_1_sclk_m__0__HSIOM_SPI EQU 15
SPI_1_sclk_m__0__HSIOM_SPI_CLK EQU 15
SPI_1_sclk_m__0__HSIOM_UART EQU 9
SPI_1_sclk_m__0__HSIOM_UART_CTS EQU 9
SPI_1_sclk_m__0__INTCFG EQU CYREG_GPIO_PRT4_INTR_CFG
SPI_1_sclk_m__0__INTR EQU CYREG_GPIO_PRT4_INTR
SPI_1_sclk_m__0__INTR_CFG EQU CYREG_GPIO_PRT4_INTR_CFG
SPI_1_sclk_m__0__INTSTAT EQU CYREG_GPIO_PRT4_INTR
SPI_1_sclk_m__0__MASK EQU 0x04
SPI_1_sclk_m__0__PC EQU CYREG_GPIO_PRT4_PC
SPI_1_sclk_m__0__PC2 EQU CYREG_GPIO_PRT4_PC2
SPI_1_sclk_m__0__PORT EQU 4
SPI_1_sclk_m__0__PS EQU CYREG_GPIO_PRT4_PS
SPI_1_sclk_m__0__SHIFT EQU 2
SPI_1_sclk_m__DR EQU CYREG_GPIO_PRT4_DR
SPI_1_sclk_m__DR_CLR EQU CYREG_GPIO_PRT4_DR_CLR
SPI_1_sclk_m__DR_INV EQU CYREG_GPIO_PRT4_DR_INV
SPI_1_sclk_m__DR_SET EQU CYREG_GPIO_PRT4_DR_SET
SPI_1_sclk_m__INTCFG EQU CYREG_GPIO_PRT4_INTR_CFG
SPI_1_sclk_m__INTR EQU CYREG_GPIO_PRT4_INTR
SPI_1_sclk_m__INTR_CFG EQU CYREG_GPIO_PRT4_INTR_CFG
SPI_1_sclk_m__INTSTAT EQU CYREG_GPIO_PRT4_INTR
SPI_1_sclk_m__MASK EQU 0x04
SPI_1_sclk_m__PC EQU CYREG_GPIO_PRT4_PC
SPI_1_sclk_m__PC2 EQU CYREG_GPIO_PRT4_PC2
SPI_1_sclk_m__PORT EQU 4
SPI_1_sclk_m__PS EQU CYREG_GPIO_PRT4_PS
SPI_1_sclk_m__SHIFT EQU 2

/* UART_1 */
UART_1_rx_wake__0__DR EQU CYREG_GPIO_PRT3_DR
UART_1_rx_wake__0__DR_CLR EQU CYREG_GPIO_PRT3_DR_CLR
UART_1_rx_wake__0__DR_INV EQU CYREG_GPIO_PRT3_DR_INV
UART_1_rx_wake__0__DR_SET EQU CYREG_GPIO_PRT3_DR_SET
UART_1_rx_wake__0__HSIOM EQU CYREG_HSIOM_PORT_SEL3
UART_1_rx_wake__0__HSIOM_GPIO EQU 0
UART_1_rx_wake__0__HSIOM_I2C EQU 14
UART_1_rx_wake__0__HSIOM_I2C_SCL EQU 14
UART_1_rx_wake__0__HSIOM_MASK EQU 0x0000000F
UART_1_rx_wake__0__HSIOM_SHIFT EQU 0
UART_1_rx_wake__0__HSIOM_SPI EQU 15
UART_1_rx_wake__0__HSIOM_SPI_MOSI EQU 15
UART_1_rx_wake__0__HSIOM_UART EQU 9
UART_1_rx_wake__0__HSIOM_UART_RX EQU 9
UART_1_rx_wake__0__INTCFG EQU CYREG_GPIO_PRT3_INTR_CFG
UART_1_rx_wake__0__INTR EQU CYREG_GPIO_PRT3_INTR
UART_1_rx_wake__0__INTR_CFG EQU CYREG_GPIO_PRT3_INTR_CFG
UART_1_rx_wake__0__INTSTAT EQU CYREG_GPIO_PRT3_INTR
UART_1_rx_wake__0__MASK EQU 0x01
UART_1_rx_wake__0__PC EQU CYREG_GPIO_PRT3_PC
UART_1_rx_wake__0__PC2 EQU CYREG_GPIO_PRT3_PC2
UART_1_rx_wake__0__PORT EQU 3
UART_1_rx_wake__0__PS EQU CYREG_GPIO_PRT3_PS
UART_1_rx_wake__0__SHIFT EQU 0
UART_1_rx_wake__DR EQU CYREG_GPIO_PRT3_DR
UART_1_rx_wake__DR_CLR EQU CYREG_GPIO_PRT3_DR_CLR
UART_1_rx_wake__DR_INV EQU CYREG_GPIO_PRT3_DR_INV
UART_1_rx_wake__DR_SET EQU CYREG_GPIO_PRT3_DR_SET
UART_1_rx_wake__INTCFG EQU CYREG_GPIO_PRT3_INTR_CFG
UART_1_rx_wake__INTR EQU CYREG_GPIO_PRT3_INTR
UART_1_rx_wake__INTR_CFG EQU CYREG_GPIO_PRT3_INTR_CFG
UART_1_rx_wake__INTSTAT EQU CYREG_GPIO_PRT3_INTR
UART_1_rx_wake__MASK EQU 0x01
UART_1_rx_wake__PC EQU CYREG_GPIO_PRT3_PC
UART_1_rx_wake__PC2 EQU CYREG_GPIO_PRT3_PC2
UART_1_rx_wake__PORT EQU 3
UART_1_rx_wake__PS EQU CYREG_GPIO_PRT3_PS
UART_1_rx_wake__SHIFT EQU 0
UART_1_rx_wake__SNAP EQU CYREG_GPIO_PRT3_INTR
UART_1_RX_WAKEUP_IRQ__INTC_CLR_EN_REG EQU CYREG_CM0P_ICER
UART_1_RX_WAKEUP_IRQ__INTC_CLR_PD_REG EQU CYREG_CM0P_ICPR
UART_1_RX_WAKEUP_IRQ__INTC_MASK EQU 0x08
UART_1_RX_WAKEUP_IRQ__INTC_NUMBER EQU 3
UART_1_RX_WAKEUP_IRQ__INTC_PRIOR_MASK EQU 0xC0000000
UART_1_RX_WAKEUP_IRQ__INTC_PRIOR_NUM EQU 3
UART_1_RX_WAKEUP_IRQ__INTC_PRIOR_REG EQU CYREG_CM0P_IPR0
UART_1_RX_WAKEUP_IRQ__INTC_SET_EN_REG EQU CYREG_CM0P_ISER
UART_1_RX_WAKEUP_IRQ__INTC_SET_PD_REG EQU CYREG_CM0P_ISPR
UART_1_SCB__CTRL EQU CYREG_SCB1_CTRL
UART_1_SCB__EZ_DATA0 EQU CYREG_SCB1_EZ_DATA0
UART_1_SCB__EZ_DATA1 EQU CYREG_SCB1_EZ_DATA1
UART_1_SCB__EZ_DATA10 EQU CYREG_SCB1_EZ_DATA10
UART_1_SCB__EZ_DATA11 EQU CYREG_SCB1_EZ_DATA11
UART_1_SCB__EZ_DATA12 EQU CYREG_SCB1_EZ_DATA12
UART_1_SCB__EZ_DATA13 EQU CYREG_SCB1_EZ_DATA13
UART_1_SCB__EZ_DATA14 EQU CYREG_SCB1_EZ_DATA14
UART_1_SCB__EZ_DATA15 EQU CYREG_SCB1_EZ_DATA15
UART_1_SCB__EZ_DATA16 EQU CYREG_SCB1_EZ_DATA16
UART_1_SCB__EZ_DATA17 EQU CYREG_SCB1_EZ_DATA17
UART_1_SCB__EZ_DATA18 EQU CYREG_SCB1_EZ_DATA18
UART_1_SCB__EZ_DATA19 EQU CYREG_SCB1_EZ_DATA19
UART_1_SCB__EZ_DATA2 EQU CYREG_SCB1_EZ_DATA2
UART_1_SCB__EZ_DATA20 EQU CYREG_SCB1_EZ_DATA20
UART_1_SCB__EZ_DATA21 EQU CYREG_SCB1_EZ_DATA21
UART_1_SCB__EZ_DATA22 EQU CYREG_SCB1_EZ_DATA22
UART_1_SCB__EZ_DATA23 EQU CYREG_SCB1_EZ_DATA23
UART_1_SCB__EZ_DATA24 EQU CYREG_SCB1_EZ_DATA24
UART_1_SCB__EZ_DATA25 EQU CYREG_SCB1_EZ_DATA25
UART_1_SCB__EZ_DATA26 EQU CYREG_SCB1_EZ_DATA26
UART_1_SCB__EZ_DATA27 EQU CYREG_SCB1_EZ_DATA27
UART_1_SCB__EZ_DATA28 EQU CYREG_SCB1_EZ_DATA28
UART_1_SCB__EZ_DATA29 EQU CYREG_SCB1_EZ_DATA29
UART_1_SCB__EZ_DATA3 EQU CYREG_SCB1_EZ_DATA3
UART_1_SCB__EZ_DATA30 EQU CYREG_SCB1_EZ_DATA30
UART_1_SCB__EZ_DATA31 EQU CYREG_SCB1_EZ_DATA31
UART_1_SCB__EZ_DATA4 EQU CYREG_SCB1_EZ_DATA4
UART_1_SCB__EZ_DATA5 EQU CYREG_SCB1_EZ_DATA5
UART_1_SCB__EZ_DATA6 EQU CYREG_SCB1_EZ_DATA6
UART_1_SCB__EZ_DATA7 EQU CYREG_SCB1_EZ_DATA7
UART_1_SCB__EZ_DATA8 EQU CYREG_SCB1_EZ_DATA8
UART_1_SCB__EZ_DATA9 EQU CYREG_SCB1_EZ_DATA9
UART_1_SCB__I2C_CFG EQU CYREG_SCB1_I2C_CFG
UART_1_SCB__I2C_CTRL EQU CYREG_SCB1_I2C_CTRL
UART_1_SCB__I2C_M_CMD EQU CYREG_SCB1_I2C_M_CMD
UART_1_SCB__I2C_S_CMD EQU CYREG_SCB1_I2C_S_CMD
UART_1_SCB__I2C_STATUS EQU CYREG_SCB1_I2C_STATUS
UART_1_SCB__INTR_CAUSE EQU CYREG_SCB1_INTR_CAUSE
UART_1_SCB__INTR_I2C_EC EQU CYREG_SCB1_INTR_I2C_EC
UART_1_SCB__INTR_I2C_EC_MASK EQU CYREG_SCB1_INTR_I2C_EC_MASK
UART_1_SCB__INTR_I2C_EC_MASKED EQU CYREG_SCB1_INTR_I2C_EC_MASKED
UART_1_SCB__INTR_M EQU CYREG_SCB1_INTR_M
UART_1_SCB__INTR_M_MASK EQU CYREG_SCB1_INTR_M_MASK
UART_1_SCB__INTR_M_MASKED EQU CYREG_SCB1_INTR_M_MASKED
UART_1_SCB__INTR_M_SET EQU CYREG_SCB1_INTR_M_SET
UART_1_SCB__INTR_RX EQU CYREG_SCB1_INTR_RX
UART_1_SCB__INTR_RX_MASK EQU CYREG_SCB1_INTR_RX_MASK
UART_1_SCB__INTR_RX_MASKED EQU CYREG_SCB1_INTR_RX_MASKED
UART_1_SCB__INTR_RX_SET EQU CYREG_SCB1_INTR_RX_SET
UART_1_SCB__INTR_S EQU CYREG_SCB1_INTR_S
UART_1_SCB__INTR_S_MASK EQU CYREG_SCB1_INTR_S_MASK
UART_1_SCB__INTR_S_MASKED EQU CYREG_SCB1_INTR_S_MASKED
UART_1_SCB__INTR_S_SET EQU CYREG_SCB1_INTR_S_SET
UART_1_SCB__INTR_SPI_EC EQU CYREG_SCB1_INTR_SPI_EC
UART_1_SCB__INTR_SPI_EC_MASK EQU CYREG_SCB1_INTR_SPI_EC_MASK
UART_1_SCB__INTR_SPI_EC_MASKED EQU CYREG_SCB1_INTR_SPI_EC_MASKED
UART_1_SCB__INTR_TX EQU CYREG_SCB1_INTR_TX
UART_1_SCB__INTR_TX_MASK EQU CYREG_SCB1_INTR_TX_MASK
UART_1_SCB__INTR_TX_MASKED EQU CYREG_SCB1_INTR_TX_MASKED
UART_1_SCB__INTR_TX_SET EQU CYREG_SCB1_INTR_TX_SET
UART_1_SCB__RX_CTRL EQU CYREG_SCB1_RX_CTRL
UART_1_SCB__RX_FIFO_CTRL EQU CYREG_SCB1_RX_FIFO_CTRL
UART_1_SCB__RX_FIFO_RD EQU CYREG_SCB1_RX_FIFO_RD
UART_1_SCB__RX_FIFO_RD_SILENT EQU CYREG_SCB1_RX_FIFO_RD_SILENT
UART_1_SCB__RX_FIFO_STATUS EQU CYREG_SCB1_RX_FIFO_STATUS
UART_1_SCB__RX_MATCH EQU CYREG_SCB1_RX_MATCH
UART_1_SCB__SPI_CTRL EQU CYREG_SCB1_SPI_CTRL
UART_1_SCB__SPI_STATUS EQU CYREG_SCB1_SPI_STATUS
UART_1_SCB__SS0_POSISTION EQU 0
UART_1_SCB__SS1_POSISTION EQU 1
UART_1_SCB__SS2_POSISTION EQU 2
UART_1_SCB__SS3_POSISTION EQU 3
UART_1_SCB__STATUS EQU CYREG_SCB1_STATUS
UART_1_SCB__TX_CTRL EQU CYREG_SCB1_TX_CTRL
UART_1_SCB__TX_FIFO_CTRL EQU CYREG_SCB1_TX_FIFO_CTRL
UART_1_SCB__TX_FIFO_STATUS EQU CYREG_SCB1_TX_FIFO_STATUS
UART_1_SCB__TX_FIFO_WR EQU CYREG_SCB1_TX_FIFO_WR
UART_1_SCB__UART_CTRL EQU CYREG_SCB1_UART_CTRL
UART_1_SCB__UART_FLOW_CTRL EQU CYREG_SCB1_UART_FLOW_CTRL
UART_1_SCB__UART_RX_CTRL EQU CYREG_SCB1_UART_RX_CTRL
UART_1_SCB__UART_RX_STATUS EQU CYREG_SCB1_UART_RX_STATUS
UART_1_SCB__UART_TX_CTRL EQU CYREG_SCB1_UART_TX_CTRL
UART_1_SCB_IRQ__INTC_CLR_EN_REG EQU CYREG_CM0P_ICER
UART_1_SCB_IRQ__INTC_CLR_PD_REG EQU CYREG_CM0P_ICPR
UART_1_SCB_IRQ__INTC_MASK EQU 0x100
UART_1_SCB_IRQ__INTC_NUMBER EQU 8
UART_1_SCB_IRQ__INTC_PRIOR_MASK EQU 0xC0
UART_1_SCB_IRQ__INTC_PRIOR_NUM EQU 0
UART_1_SCB_IRQ__INTC_PRIOR_REG EQU CYREG_CM0P_IPR2
UART_1_SCB_IRQ__INTC_SET_EN_REG EQU CYREG_CM0P_ISER
UART_1_SCB_IRQ__INTC_SET_PD_REG EQU CYREG_CM0P_ISPR
UART_1_SCBCLK__CTRL_REGISTER EQU CYREG_PERI_PCLK_CTL1
UART_1_SCBCLK__DIV_ID EQU 0x00000041
UART_1_SCBCLK__DIV_REGISTER EQU CYREG_PERI_DIV_16_CTL1
UART_1_SCBCLK__PA_DIV_ID EQU 0x000000FF
UART_1_tx__0__DR EQU CYREG_GPIO_PRT3_DR
UART_1_tx__0__DR_CLR EQU CYREG_GPIO_PRT3_DR_CLR
UART_1_tx__0__DR_INV EQU CYREG_GPIO_PRT3_DR_INV
UART_1_tx__0__DR_SET EQU CYREG_GPIO_PRT3_DR_SET
UART_1_tx__0__HSIOM EQU CYREG_HSIOM_PORT_SEL3
UART_1_tx__0__HSIOM_GPIO EQU 0
UART_1_tx__0__HSIOM_I2C EQU 14
UART_1_tx__0__HSIOM_I2C_SDA EQU 14
UART_1_tx__0__HSIOM_MASK EQU 0x000000F0
UART_1_tx__0__HSIOM_SHIFT EQU 4
UART_1_tx__0__HSIOM_SPI EQU 15
UART_1_tx__0__HSIOM_SPI_MISO EQU 15
UART_1_tx__0__HSIOM_UART EQU 9
UART_1_tx__0__HSIOM_UART_TX EQU 9
UART_1_tx__0__INTCFG EQU CYREG_GPIO_PRT3_INTR_CFG
UART_1_tx__0__INTR EQU CYREG_GPIO_PRT3_INTR
UART_1_tx__0__INTR_CFG EQU CYREG_GPIO_PRT3_INTR_CFG
UART_1_tx__0__INTSTAT EQU CYREG_GPIO_PRT3_INTR
UART_1_tx__0__MASK EQU 0x02
UART_1_tx__0__PC EQU CYREG_GPIO_PRT3_PC
UART_1_tx__0__PC2 EQU CYREG_GPIO_PRT3_PC2
UART_1_tx__0__PORT EQU 3
UART_1_tx__0__PS EQU CYREG_GPIO_PRT3_PS
UART_1_tx__0__SHIFT EQU 1
UART_1_tx__DR EQU CYREG_GPIO_PRT3_DR
UART_1_tx__DR_CLR EQU CYREG_GPIO_PRT3_DR_CLR
UART_1_tx__DR_INV EQU CYREG_GPIO_PRT3_DR_INV
UART_1_tx__DR_SET EQU CYREG_GPIO_PRT3_DR_SET
UART_1_tx__INTCFG EQU CYREG_GPIO_PRT3_INTR_CFG
UART_1_tx__INTR EQU CYREG_GPIO_PRT3_INTR
UART_1_tx__INTR_CFG EQU CYREG_GPIO_PRT3_INTR_CFG
UART_1_tx__INTSTAT EQU CYREG_GPIO_PRT3_INTR
UART_1_tx__MASK EQU 0x02
UART_1_tx__PC EQU CYREG_GPIO_PRT3_PC
UART_1_tx__PC2 EQU CYREG_GPIO_PRT3_PC2
UART_1_tx__PORT EQU 3
UART_1_tx__PS EQU CYREG_GPIO_PRT3_PS
UART_1_tx__SHIFT EQU 1

/* antpow */
antpow__0__DR EQU CYREG_GPIO_PRT6_DR
antpow__0__DR_CLR EQU CYREG_GPIO_PRT6_DR_CLR
antpow__0__DR_INV EQU CYREG_GPIO_PRT6_DR_INV
antpow__0__DR_SET EQU CYREG_GPIO_PRT6_DR_SET
antpow__0__HSIOM EQU CYREG_HSIOM_PORT_SEL6
antpow__0__HSIOM_MASK EQU 0x000000F0
antpow__0__HSIOM_SHIFT EQU 4
antpow__0__INTCFG EQU CYREG_GPIO_PRT6_INTR_CFG
antpow__0__INTR EQU CYREG_GPIO_PRT6_INTR
antpow__0__INTR_CFG EQU CYREG_GPIO_PRT6_INTR_CFG
antpow__0__INTSTAT EQU CYREG_GPIO_PRT6_INTR
antpow__0__MASK EQU 0x02
antpow__0__PC EQU CYREG_GPIO_PRT6_PC
antpow__0__PC2 EQU CYREG_GPIO_PRT6_PC2
antpow__0__PORT EQU 6
antpow__0__PS EQU CYREG_GPIO_PRT6_PS
antpow__0__SHIFT EQU 1
antpow__DR EQU CYREG_GPIO_PRT6_DR
antpow__DR_CLR EQU CYREG_GPIO_PRT6_DR_CLR
antpow__DR_INV EQU CYREG_GPIO_PRT6_DR_INV
antpow__DR_SET EQU CYREG_GPIO_PRT6_DR_SET
antpow__INTCFG EQU CYREG_GPIO_PRT6_INTR_CFG
antpow__INTR EQU CYREG_GPIO_PRT6_INTR
antpow__INTR_CFG EQU CYREG_GPIO_PRT6_INTR_CFG
antpow__INTSTAT EQU CYREG_GPIO_PRT6_INTR
antpow__MASK EQU 0x02
antpow__PC EQU CYREG_GPIO_PRT6_PC
antpow__PC2 EQU CYREG_GPIO_PRT6_PC2
antpow__PORT EQU 6
antpow__PS EQU CYREG_GPIO_PRT6_PS
antpow__SHIFT EQU 1

/* SPI_BUSY */
SPI_BUSY__0__DR EQU CYREG_GPIO_PRT4_DR
SPI_BUSY__0__DR_CLR EQU CYREG_GPIO_PRT4_DR_CLR
SPI_BUSY__0__DR_INV EQU CYREG_GPIO_PRT4_DR_INV
SPI_BUSY__0__DR_SET EQU CYREG_GPIO_PRT4_DR_SET
SPI_BUSY__0__HSIOM EQU CYREG_HSIOM_PORT_SEL4
SPI_BUSY__0__HSIOM_MASK EQU 0xF0000000
SPI_BUSY__0__HSIOM_SHIFT EQU 28
SPI_BUSY__0__INTCFG EQU CYREG_GPIO_PRT4_INTR_CFG
SPI_BUSY__0__INTR EQU CYREG_GPIO_PRT4_INTR
SPI_BUSY__0__INTR_CFG EQU CYREG_GPIO_PRT4_INTR_CFG
SPI_BUSY__0__INTSTAT EQU CYREG_GPIO_PRT4_INTR
SPI_BUSY__0__MASK EQU 0x80
SPI_BUSY__0__PC EQU CYREG_GPIO_PRT4_PC
SPI_BUSY__0__PC2 EQU CYREG_GPIO_PRT4_PC2
SPI_BUSY__0__PORT EQU 4
SPI_BUSY__0__PS EQU CYREG_GPIO_PRT4_PS
SPI_BUSY__0__SHIFT EQU 7
SPI_BUSY__DR EQU CYREG_GPIO_PRT4_DR
SPI_BUSY__DR_CLR EQU CYREG_GPIO_PRT4_DR_CLR
SPI_BUSY__DR_INV EQU CYREG_GPIO_PRT4_DR_INV
SPI_BUSY__DR_SET EQU CYREG_GPIO_PRT4_DR_SET
SPI_BUSY__INTCFG EQU CYREG_GPIO_PRT4_INTR_CFG
SPI_BUSY__INTR EQU CYREG_GPIO_PRT4_INTR
SPI_BUSY__INTR_CFG EQU CYREG_GPIO_PRT4_INTR_CFG
SPI_BUSY__INTSTAT EQU CYREG_GPIO_PRT4_INTR
SPI_BUSY__MASK EQU 0x80
SPI_BUSY__PC EQU CYREG_GPIO_PRT4_PC
SPI_BUSY__PC2 EQU CYREG_GPIO_PRT4_PC2
SPI_BUSY__PORT EQU 4
SPI_BUSY__PS EQU CYREG_GPIO_PRT4_PS
SPI_BUSY__SHIFT EQU 7

/* SPI_NRESET */
SPI_NRESET__0__DR EQU CYREG_GPIO_PRT5_DR
SPI_NRESET__0__DR_CLR EQU CYREG_GPIO_PRT5_DR_CLR
SPI_NRESET__0__DR_INV EQU CYREG_GPIO_PRT5_DR_INV
SPI_NRESET__0__DR_SET EQU CYREG_GPIO_PRT5_DR_SET
SPI_NRESET__0__HSIOM EQU CYREG_HSIOM_PORT_SEL5
SPI_NRESET__0__HSIOM_MASK EQU 0xF0000000
SPI_NRESET__0__HSIOM_SHIFT EQU 28
SPI_NRESET__0__INTCFG EQU CYREG_GPIO_PRT5_INTR_CFG
SPI_NRESET__0__INTR EQU CYREG_GPIO_PRT5_INTR
SPI_NRESET__0__INTR_CFG EQU CYREG_GPIO_PRT5_INTR_CFG
SPI_NRESET__0__INTSTAT EQU CYREG_GPIO_PRT5_INTR
SPI_NRESET__0__MASK EQU 0x80
SPI_NRESET__0__PC EQU CYREG_GPIO_PRT5_PC
SPI_NRESET__0__PC2 EQU CYREG_GPIO_PRT5_PC2
SPI_NRESET__0__PORT EQU 5
SPI_NRESET__0__PS EQU CYREG_GPIO_PRT5_PS
SPI_NRESET__0__SHIFT EQU 7
SPI_NRESET__DR EQU CYREG_GPIO_PRT5_DR
SPI_NRESET__DR_CLR EQU CYREG_GPIO_PRT5_DR_CLR
SPI_NRESET__DR_INV EQU CYREG_GPIO_PRT5_DR_INV
SPI_NRESET__DR_SET EQU CYREG_GPIO_PRT5_DR_SET
SPI_NRESET__INTCFG EQU CYREG_GPIO_PRT5_INTR_CFG
SPI_NRESET__INTR EQU CYREG_GPIO_PRT5_INTR
SPI_NRESET__INTR_CFG EQU CYREG_GPIO_PRT5_INTR_CFG
SPI_NRESET__INTSTAT EQU CYREG_GPIO_PRT5_INTR
SPI_NRESET__MASK EQU 0x80
SPI_NRESET__PC EQU CYREG_GPIO_PRT5_PC
SPI_NRESET__PC2 EQU CYREG_GPIO_PRT5_PC2
SPI_NRESET__PORT EQU 5
SPI_NRESET__PS EQU CYREG_GPIO_PRT5_PS
SPI_NRESET__SHIFT EQU 7

/* global_irq */
global_irq__INTC_CLR_EN_REG EQU CYREG_CM0P_ICER
global_irq__INTC_CLR_PD_REG EQU CYREG_CM0P_ICPR
global_irq__INTC_MASK EQU 0x10
global_irq__INTC_NUMBER EQU 4
global_irq__INTC_PRIOR_MASK EQU 0xC0
global_irq__INTC_PRIOR_NUM EQU 2
global_irq__INTC_PRIOR_REG EQU CYREG_CM0P_IPR1
global_irq__INTC_SET_EN_REG EQU CYREG_CM0P_ISER
global_irq__INTC_SET_PD_REG EQU CYREG_CM0P_ISPR

/* pin_wakeup */
pin_wakeup__0__DR EQU CYREG_GPIO_PRT0_DR
pin_wakeup__0__DR_CLR EQU CYREG_GPIO_PRT0_DR_CLR
pin_wakeup__0__DR_INV EQU CYREG_GPIO_PRT0_DR_INV
pin_wakeup__0__DR_SET EQU CYREG_GPIO_PRT0_DR_SET
pin_wakeup__0__HSIOM EQU CYREG_HSIOM_PORT_SEL0
pin_wakeup__0__HSIOM_MASK EQU 0x00000F00
pin_wakeup__0__HSIOM_SHIFT EQU 8
pin_wakeup__0__INTCFG EQU CYREG_GPIO_PRT0_INTR_CFG
pin_wakeup__0__INTR EQU CYREG_GPIO_PRT0_INTR
pin_wakeup__0__INTR_CFG EQU CYREG_GPIO_PRT0_INTR_CFG
pin_wakeup__0__INTSTAT EQU CYREG_GPIO_PRT0_INTR
pin_wakeup__0__MASK EQU 0x04
pin_wakeup__0__PC EQU CYREG_GPIO_PRT0_PC
pin_wakeup__0__PC2 EQU CYREG_GPIO_PRT0_PC2
pin_wakeup__0__PORT EQU 0
pin_wakeup__0__PS EQU CYREG_GPIO_PRT0_PS
pin_wakeup__0__SHIFT EQU 2
pin_wakeup__DR EQU CYREG_GPIO_PRT0_DR
pin_wakeup__DR_CLR EQU CYREG_GPIO_PRT0_DR_CLR
pin_wakeup__DR_INV EQU CYREG_GPIO_PRT0_DR_INV
pin_wakeup__DR_SET EQU CYREG_GPIO_PRT0_DR_SET
pin_wakeup__INTCFG EQU CYREG_GPIO_PRT0_INTR_CFG
pin_wakeup__INTR EQU CYREG_GPIO_PRT0_INTR
pin_wakeup__INTR_CFG EQU CYREG_GPIO_PRT0_INTR_CFG
pin_wakeup__INTSTAT EQU CYREG_GPIO_PRT0_INTR
pin_wakeup__MASK EQU 0x04
pin_wakeup__PC EQU CYREG_GPIO_PRT0_PC
pin_wakeup__PC2 EQU CYREG_GPIO_PRT0_PC2
pin_wakeup__PORT EQU 0
pin_wakeup__PS EQU CYREG_GPIO_PRT0_PS
pin_wakeup__SHIFT EQU 2
pin_wakeup__SNAP EQU CYREG_GPIO_PRT0_INTR

/* wakeup_irq */
wakeup_irq__INTC_CLR_EN_REG EQU CYREG_CM0P_ICER
wakeup_irq__INTC_CLR_PD_REG EQU CYREG_CM0P_ICPR
wakeup_irq__INTC_MASK EQU 0x01
wakeup_irq__INTC_NUMBER EQU 0
wakeup_irq__INTC_PRIOR_MASK EQU 0xC0
wakeup_irq__INTC_PRIOR_NUM EQU 3
wakeup_irq__INTC_PRIOR_REG EQU CYREG_CM0P_IPR0
wakeup_irq__INTC_SET_EN_REG EQU CYREG_CM0P_ISER
wakeup_irq__INTC_SET_PD_REG EQU CYREG_CM0P_ISPR

/* Miscellaneous */
CYDEV_BCLK__HFCLK__HZ EQU 24000000
CYDEV_BCLK__HFCLK__KHZ EQU 24000
CYDEV_BCLK__HFCLK__MHZ EQU 24
CYDEV_BCLK__SYSCLK__HZ EQU 24000000
CYDEV_BCLK__SYSCLK__KHZ EQU 24000
CYDEV_BCLK__SYSCLK__MHZ EQU 24
CYDEV_CHIP_DIE_LEOPARD EQU 1
CYDEV_CHIP_DIE_PSOC4A EQU 18
CYDEV_CHIP_DIE_PSOC5LP EQU 2
CYDEV_CHIP_DIE_PSOC5TM EQU 3
CYDEV_CHIP_DIE_TMA4 EQU 4
CYDEV_CHIP_DIE_UNKNOWN EQU 0
CYDEV_CHIP_FAMILY_FM0P EQU 5
CYDEV_CHIP_FAMILY_FM3 EQU 6
CYDEV_CHIP_FAMILY_FM4 EQU 7
CYDEV_CHIP_FAMILY_PSOC3 EQU 1
CYDEV_CHIP_FAMILY_PSOC4 EQU 2
CYDEV_CHIP_FAMILY_PSOC5 EQU 3
CYDEV_CHIP_FAMILY_PSOC6 EQU 4
CYDEV_CHIP_FAMILY_UNKNOWN EQU 0
CYDEV_CHIP_FAMILY_USED EQU CYDEV_CHIP_FAMILY_PSOC4
CYDEV_CHIP_JTAG_ID EQU 0x256A11B5
CYDEV_CHIP_MEMBER_3A EQU 1
CYDEV_CHIP_MEMBER_4A EQU 18
CYDEV_CHIP_MEMBER_4D EQU 13
CYDEV_CHIP_MEMBER_4E EQU 6
CYDEV_CHIP_MEMBER_4F EQU 19
CYDEV_CHIP_MEMBER_4G EQU 4
CYDEV_CHIP_MEMBER_4H EQU 17
CYDEV_CHIP_MEMBER_4I EQU 23
CYDEV_CHIP_MEMBER_4J EQU 14
CYDEV_CHIP_MEMBER_4K EQU 15
CYDEV_CHIP_MEMBER_4L EQU 22
CYDEV_CHIP_MEMBER_4M EQU 21
CYDEV_CHIP_MEMBER_4N EQU 10
CYDEV_CHIP_MEMBER_4O EQU 7
CYDEV_CHIP_MEMBER_4P EQU 20
CYDEV_CHIP_MEMBER_4Q EQU 12
CYDEV_CHIP_MEMBER_4R EQU 8
CYDEV_CHIP_MEMBER_4S EQU 11
CYDEV_CHIP_MEMBER_4T EQU 9
CYDEV_CHIP_MEMBER_4U EQU 5
CYDEV_CHIP_MEMBER_4V EQU 16
CYDEV_CHIP_MEMBER_5A EQU 3
CYDEV_CHIP_MEMBER_5B EQU 2
CYDEV_CHIP_MEMBER_6A EQU 24
CYDEV_CHIP_MEMBER_FM3 EQU 28
CYDEV_CHIP_MEMBER_FM4 EQU 29
CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE1 EQU 25
CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE2 EQU 26
CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE3 EQU 27
CYDEV_CHIP_MEMBER_UNKNOWN EQU 0
CYDEV_CHIP_MEMBER_USED EQU CYDEV_CHIP_MEMBER_4V
CYDEV_CHIP_DIE_EXPECT EQU CYDEV_CHIP_MEMBER_USED
CYDEV_CHIP_DIE_ACTUAL EQU CYDEV_CHIP_DIE_EXPECT
CYDEV_CHIP_REV_LEOPARD_ES1 EQU 0
CYDEV_CHIP_REV_LEOPARD_ES2 EQU 1
CYDEV_CHIP_REV_LEOPARD_ES3 EQU 3
CYDEV_CHIP_REV_LEOPARD_PRODUCTION EQU 3
CYDEV_CHIP_REV_PSOC4A_ES0 EQU 17
CYDEV_CHIP_REV_PSOC4A_PRODUCTION EQU 17
CYDEV_CHIP_REV_PSOC5LP_ES0 EQU 0
CYDEV_CHIP_REV_PSOC5LP_PRODUCTION EQU 0
CYDEV_CHIP_REV_PSOC5TM_ES0 EQU 0
CYDEV_CHIP_REV_PSOC5TM_ES1 EQU 1
CYDEV_CHIP_REV_PSOC5TM_PRODUCTION EQU 1
CYDEV_CHIP_REV_TMA4_ES EQU 17
CYDEV_CHIP_REV_TMA4_ES2 EQU 33
CYDEV_CHIP_REV_TMA4_PRODUCTION EQU 17
CYDEV_CHIP_REVISION_3A_ES1 EQU 0
CYDEV_CHIP_REVISION_3A_ES2 EQU 1
CYDEV_CHIP_REVISION_3A_ES3 EQU 3
CYDEV_CHIP_REVISION_3A_PRODUCTION EQU 3
CYDEV_CHIP_REVISION_4A_ES0 EQU 17
CYDEV_CHIP_REVISION_4A_PRODUCTION EQU 17
CYDEV_CHIP_REVISION_4D_PRODUCTION EQU 0
CYDEV_CHIP_REVISION_4E_CCG2_NO_USBPD EQU 0
CYDEV_CHIP_REVISION_4E_PRODUCTION EQU 0
CYDEV_CHIP_REVISION_4F_PRODUCTION EQU 0
CYDEV_CHIP_REVISION_4F_PRODUCTION_256DMA EQU 0
CYDEV_CHIP_REVISION_4F_PRODUCTION_256K EQU 0
CYDEV_CHIP_REVISION_4G_ES EQU 17
CYDEV_CHIP_REVISION_4G_ES2 EQU 33
CYDEV_CHIP_REVISION_4G_PRODUCTION EQU 17
CYDEV_CHIP_REVISION_4H_PRODUCTION EQU 0
CYDEV_CHIP_REVISION_4I_PRODUCTION EQU 0
CYDEV_CHIP_REVISION_4J_PRODUCTION EQU 0
CYDEV_CHIP_REVISION_4K_PRODUCTION EQU 0
CYDEV_CHIP_REVISION_4L_PRODUCTION EQU 0
CYDEV_CHIP_REVISION_4M_PRODUCTION EQU 0
CYDEV_CHIP_REVISION_4N_PRODUCTION EQU 0
CYDEV_CHIP_REVISION_4O_PRODUCTION EQU 0
CYDEV_CHIP_REVISION_4P_PRODUCTION EQU 0
CYDEV_CHIP_REVISION_4Q_PRODUCTION EQU 0
CYDEV_CHIP_REVISION_4R_PRODUCTION EQU 0
CYDEV_CHIP_REVISION_4S_PRODUCTION EQU 0
CYDEV_CHIP_REVISION_4T_PRODUCTION EQU 0
CYDEV_CHIP_REVISION_4U_PRODUCTION EQU 0
CYDEV_CHIP_REVISION_4V_PRODUCTION EQU 0
CYDEV_CHIP_REVISION_5A_ES0 EQU 0
CYDEV_CHIP_REVISION_5A_ES1 EQU 1
CYDEV_CHIP_REVISION_5A_PRODUCTION EQU 1
CYDEV_CHIP_REVISION_5B_ES0 EQU 0
CYDEV_CHIP_REVISION_5B_PRODUCTION EQU 0
CYDEV_CHIP_REVISION_6A_ES EQU 17
CYDEV_CHIP_REVISION_6A_NO_UDB EQU 33
CYDEV_CHIP_REVISION_6A_PRODUCTION EQU 33
CYDEV_CHIP_REVISION_FM3_PRODUCTION EQU 0
CYDEV_CHIP_REVISION_FM4_PRODUCTION EQU 0
CYDEV_CHIP_REVISION_PDL_FM0P_TYPE1_PRODUCTION EQU 0
CYDEV_CHIP_REVISION_PDL_FM0P_TYPE2_PRODUCTION EQU 0
CYDEV_CHIP_REVISION_PDL_FM0P_TYPE3_PRODUCTION EQU 0
CYDEV_CHIP_REVISION_USED EQU CYDEV_CHIP_REVISION_4V_PRODUCTION
CYDEV_CHIP_REV_EXPECT EQU CYDEV_CHIP_REVISION_USED
CYDEV_CONFIG_READ_ACCELERATOR EQU 1
CYDEV_CONFIG_UNUSED_IO_AllowButWarn EQU 0
CYDEV_CONFIG_UNUSED_IO_AllowWithInfo EQU 1
CYDEV_CONFIG_UNUSED_IO_Disallowed EQU 2
CYDEV_CONFIG_UNUSED_IO EQU CYDEV_CONFIG_UNUSED_IO_Disallowed
CYDEV_CONFIGURATION_COMPRESSED EQU 1
CYDEV_CONFIGURATION_MODE_COMPRESSED EQU 0
CYDEV_CONFIGURATION_MODE EQU CYDEV_CONFIGURATION_MODE_COMPRESSED
CYDEV_CONFIGURATION_MODE_DMA EQU 2
CYDEV_CONFIGURATION_MODE_UNCOMPRESSED EQU 1
CYDEV_DEBUG_PROTECT_KILL EQU 4
CYDEV_DEBUG_PROTECT_OPEN EQU 1
CYDEV_DEBUG_PROTECT EQU CYDEV_DEBUG_PROTECT_OPEN
CYDEV_DEBUG_PROTECT_PROTECTED EQU 2
CYDEV_DEBUGGING_DPS_Disable EQU 3
CYDEV_DEBUGGING_DPS EQU CYDEV_DEBUGGING_DPS_Disable
CYDEV_DEBUGGING_DPS_SWD EQU 2
CYDEV_DEBUGGING_ENABLE EQU 0
CYDEV_DFT_SELECT_CLK0 EQU 8
CYDEV_DFT_SELECT_CLK1 EQU 9
CYDEV_DMA_CHANNELS_AVAILABLE EQU 8
CYDEV_HEAP_SIZE EQU 0x1100
CYDEV_IMO_TRIMMED_BY_USB EQU 0
CYDEV_IMO_TRIMMED_BY_WCO EQU 0
CYDEV_INTR_NUMBER_DMA EQU 14
CYDEV_IS_EXPORTING_CODE EQU 0
CYDEV_IS_IMPORTING_CODE EQU 0
CYDEV_PROJ_TYPE EQU 0
CYDEV_PROJ_TYPE_BOOTLOADER EQU 1
CYDEV_PROJ_TYPE_LAUNCHER EQU 5
CYDEV_PROJ_TYPE_LOADABLE EQU 2
CYDEV_PROJ_TYPE_LOADABLEANDBOOTLOADER EQU 4
CYDEV_PROJ_TYPE_MULTIAPPBOOTLOADER EQU 3
CYDEV_PROJ_TYPE_STANDARD EQU 0
CYDEV_STACK_SIZE EQU 0x0080
CYDEV_USE_BUNDLED_CMSIS EQU 1
CYDEV_VARIABLE_VDDA EQU 1
CYDEV_VDDA_MV EQU 3300
CYDEV_VDDD_MV EQU 3300
CYDEV_WDT_GENERATE_ISR EQU 1
CYIPBLOCK_m0s8cpussv3_VERSION EQU 1
CYIPBLOCK_m0s8crypto_VERSION EQU 2
CYIPBLOCK_m0s8csdv2_VERSION EQU 2
CYIPBLOCK_m0s8exco_VERSION EQU 1
CYIPBLOCK_m0s8ioss_VERSION EQU 1
CYIPBLOCK_m0s8lcd_VERSION EQU 2
CYIPBLOCK_m0s8lpcomp_VERSION EQU 2
CYIPBLOCK_m0s8pass4a_VERSION EQU 1
CYIPBLOCK_m0s8peri_VERSION EQU 1
CYIPBLOCK_m0s8scb_VERSION EQU 2
CYIPBLOCK_m0s8tcpwm_VERSION EQU 2
CYIPBLOCK_m0s8wco_VERSION EQU 1
CYIPBLOCK_s8srsslt_VERSION EQU 1
DMA_CHANNELS_USED__MASK EQU 0
CYDEV_BOOTLOADER_ENABLE EQU 0

#endif /* INCLUDED_CYFITTERIAR_INC */
